**6.S186: FPGA Design "Competition"** **IAP 2020** - [MIT](http://www.mit.edu) - [Course 6](https://www.eecs.mit.edu/) **Instructors:** Gim Hom , Joe Steinmeyer Overview ======================== 6.S193 for IAP 2020 is the second offering of an FPGA competition, which we're using as an excuse to get a chance to mess with FPGAs more. Depending on your background, we're including some readings and some labs, some adapted from 6.111 run here at MIT in the fall semester. The real goal, however (or keep developing) some neat FPGA-centric projects. For this reason, we'll mostly be running office hours this IAP, helping you with projects as needed! Our thanks to Apple for providing support. Pages and References =========================== Below are a few labs and other pages we're putting together for the course. We'll probably post more as we go through. * [Notes 1](./dd1) * [Notes 2](./dd2) * [Lab 1: Vivado/Verilog Intro I](./lab1) * [Lab 2: Vivado/Verilog Intro II](./lab2) Some Reference Pages: * [6.S193 Homepage (2019 IAP Class) for reference](http://eecs6111.mit.edu/6s193/) Schedule ===================================================================== Wednesday Jan 8, 2020: Lecture 1 - [Lecture 1 ](./resources/lec1.pdf) - Open Lab Hours Thursday Jan 9, 2020: Lecture 2 - [Lecture 2 ](./resources/lec2.pdf) - Open Lab Hours Tuesday Jan 28, 2020: Final Project Stuff - Wrap-up - Careers in Hardware (4-6pm 32-141) Wednesday Jan 29, 2020: Final Project Stuff - Apple, Wrap-up There will potentially be a few one-hour lectures Mon-Thu 1-2pm-ish for two weeks starting Wed January 8 in 32-144. The lab (38-600) will be open 9am-9pm with staff available 3pm-6pm for working with the systems and projects for the first few weeks. We may extend hours/change them as the course progresses depending on everyone's needs, especially towards the end. Parts of the Site Structure and Style Rendered Using Markdeep